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CS & IT Engineering: Introduction to COA -(Registers, Instruction Cycle & GATE Questions)

By v yadav Last updated Jun 16, 2026

CS & IT Engineering: Introduction to COA - (Registers, Instruction Cycle & GATE Questions)

This article continues the exploration of Computer Organization and Architecture (COA), delving deeper into the types of CPU registers, a detailed breakdown of the instruction cycle, and practical GATE-style problems to test understanding.

Table of Contents

Topics Covered

Registers & Their Types
Instruction Cycle (Fetch & Execute)
GATE Questions & Practice Problems

1. Registers: The Fastest Storage Inside the CPU

Registers are the fastest storage locations within the CPU. They are built using Flip-Flops, where a single Flip-Flop stores 1 bit of information. An n-bit register is simply a collection of n flip-flops.

Classification Based on Task Assigned

Type	Description	Examples
General Purpose Registers (GPR)	Used for any general-purpose data processing. Programmers can use these to store intermediate results or operands.	R0, R1, R2, R3…
Special Purpose Registers (SPR)	Used for a dedicated, specific task as defined by the CPU architecture.	PC, IR, SP, MAR, MBR, AC, PSW

Classification Based on Information Stored

Address Registers: Store memory addresses.
- Program Counter (PC): Also called the Instruction Pointer or Instruction Address Register. Holds the starting address of the next instruction to be fetched. It acts like a pointer, telling the CPU where to go next.
- Memory Address Register (MAR): Holds the address of the memory location that the CPU wants to read from or write to.
- Stack Pointer (SP): Holds the address of the Top of the Stack (TOS) in memory.
Data/Instruction Registers: Store data or instructions.
- Memory Buffer Register (MBR) / Memory Data Register (MDR): Holds the actual data or instruction that has been fetched from memory or is waiting to be written to memory.
- Instruction Register (IR): Holds the instruction that is currently being executed by the CPU. It contains the Opcode (operation code, i.e., the type of operation) and the Operand (the data or the address of the data).
- Accumulator (AC): Stores temporary results of ALU operations. For example, ADD [4000] means AC ← AC + M(4000).
- Flag Register / Program Status Word (PSW): Stores status flags (e.g., Carry, Zero, Overflow) that indicate the status of the result of the last ALU operation.

2. The Instruction Cycle in Detail

Every instruction must be fetched from memory into the CPU before it can be executed. This process is known as the Instruction Cycle.

The Fetch Cycle

Objective: To fetch the next instruction from main memory to the CPU.
Process:
1. The address in the Program Counter (PC) is transferred to the Memory Address Register (MAR).
2. The CPU sends a read signal to the memory. The instruction at that address is placed in the Memory Buffer Register (MBR).
3. The instruction is moved from the MBR to the Instruction Register (IR).
4. The Program Counter (PC) is incremented so that it now points to the starting address of the next instruction.

Important: At the end of the fetch cycle, the PC is always updated.

The Execute Cycle

Objective: To process (execute) the fetched instruction.
Sub-steps: The execute cycle can be broken down into the following steps:
1. IAC (Instruction Address Calculation): The address of the next instruction is calculated (usually just incrementing the PC).
2. IF (Instruction Fetch): The instruction is fetched from memory (as described above).
3. Decoding: The CPU decodes the instruction to determine the opcode and operands.
4. OAC (Operand Address Calculation): The address of any operands is calculated.
5. OF (Operand Fetch): The operands are fetched from memory.
6. DP (Data Processing): The ALU performs the required operation.
7. Result Storage: The result is stored back in memory or a register.

The Interrupt Cycle

An interrupt is a signal that requires the CPU’s immediate attention.

When the CPU encounters an interrupt, it completes the execution of the current instruction.
It then Pushes the current Program Counter (PC) value onto the stack as a return address. This ensures the CPU can resume from where it left off after the interrupt is handled.
Control is transferred to the Interrupt Service Routine (ISR).
After the ISR is completed, the PC value is popped from the stack, and the CPU resumes execution.

3. Memory Addressability: Byte vs. Word

A crucial concept for solving problems is how memory is addressed. This determines how the Program Counter (PC) is incremented.

Feature	Byte Addressable Memory	Word Addressable Memory
Definition	Each individual byte has a unique memory address.	Each word (a group of bytes) has a unique memory address.
Addressing	The CPU can access any specific byte.	The CPU can only access data in whole words.
Address Increment	The PC is incremented by the number of bytes in the instruction.	The PC is incremented by 1 for each word.
Example	If `1 Word = 32 bits = 4 Bytes`, and `I1` is 1 word, it will occupy addresses `2000` to `2003`. The next instruction `I2` will start at `2004`.	If `I1` is 1 word, it will occupy address `2000` only. The next instruction `I2` will start at `2001`.

Memory Representation Example:

text

Byte Addressable (Word = 32 bit = 4 Byte)
| I1 (1W) | I2 (1W) | I3 (1W) |
| 2000-2003 | 2004-2007 | 2008-2011 |

Word Addressable
| I1 (1W) | I2 (1W) | I3 (1W) |
|  2000   |  2001   |  2002   |

4. Practice Problems (GATE-Style)

Let’s apply these concepts to solve typical exam questions.

Problem 1: Program Counter Value During Execution

Question: Consider a program stored in memory starting at address 1000 (decimal). During the execution of I6, what is the value in the Program Counter? Assume word size is 32 bits & memory is Byte Addressable.

Instruction	Size (in words)
I1	2
I2	1
I3	1
I4	3
I5	1
I6	2
I7	1

Solution:

Calculate Word Size in Bytes: 1 Word = 32 bits = 4 Bytes.
Calculate Starting Addresses:
- I1: 2 words = 8 bytes. Occupies 1000 - 1007. I2 starts at 1008.
- I2: 1 word = 4 bytes. Occupies 1008 - 1011. I3 starts at 1012.
- I3: 1 word = 4 bytes. Occupies 1012 - 1015. I4 starts at 1016.
- I4: 3 words = 12 bytes. Occupies 1016 - 1027. I5 starts at 1028.
- I5: 1 word = 4 bytes. Occupies 1028 - 1031. I6 starts at 1032.
- I6: 2 words = 8 bytes. Occupies 1032 - 1039. I7 starts at 1040.
During Execution of I6: The PC is incremented during the fetch cycle. When the CPU is executing I6, the PC has already been updated to point to the next instruction. Therefore, the PC holds the starting address of I7.
Answer: The value present in the Program Counter is 1040.

Problem 2: Return Address with Interrupt

Question: Consider the following program segment for a hypothetical CPU having registers R1, R2, and R3. The memory is word addressable with a size of 32 bits. The program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs during the ADD instruction, what will be the return address pushed onto the stack?

Instruction	Operation	Size (in words)
MOV R1, 5000	R1 ← Memory[5000]	2
MOV R2, (R1)	R2 ← Memory[(R1)]	1
ADD R2, R3	R2 ← R2 + R3	1
MOV 6000, R2	Memory[6000] ← R2	2
HALT	Machine Halts	1

Solution:

Identify the Interrupt Point: The interrupt occurs during the execution of the ADD instruction. Since the CPU completes the current instruction before servicing the interrupt, the CPU is executing ADD.
Program Counter (PC) Behavior: During the fetch cycle of the ADD instruction, the PC was incremented to point to the next instruction.
Find the Next Instruction: The instruction after ADD is MOV 6000, R2.
Calculate its Address:
- MOV R1, 5000 (2 words): Starts at 1000.
- MOV R2, (R1) (1 word): Starts at 1000 + 2 = 1002.
- ADD R2, R3 (1 word): Starts at 1002 + 1 = 1003.
- Next Instruction (MOV 6000, R2): Starts at 1003 + 1 = 1004.
Return Address: The return address pushed onto the stack will be the address of the next instruction to be executed, which is 1004.

Answer: (b) 1004

Problem 3: Byte Addressable with Interrupt

Question: Consider the same program but now assume memory is Byte Addressable with a size of 32 bits. If an interrupt occurs while executing the MOV 6000, R2 instruction, what will be the return address saved in the stack?

Solution:

Identify the Interrupt Point: The interrupt occurs during the execution of the MOV 6000, R2 instruction.
Program Counter (PC) Behavior: The PC is already pointing to the address of the next instruction, HALT.
Calculate the Address of HALT in Byte-Addressable Memory:
- 1 Word = 32 bits = 4 Bytes.
- MOV R1, 5000 (2 words): 2 words = 8 bytes. Occupies 1000 - 1007. Next starts at 1008.
- MOV R2, (R1) (1 word): 1 word = 4 bytes. Occupies 1008 - 1011. Next starts at 1012.
- ADD R2, R3 (1 word): 1 word = 4 bytes. Occupies 1012 - 1015. Next starts at 1016.
- MOV 6000, R2 (2 words): 2 words = 8 bytes. Occupies 1016 - 1023. Next (HALT) starts at 1024.
Answer: The return address pushed on the stack will be 1024.

Answer: (c) 1024